Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
With planar bulk Metal-Oxide Semiconductor (MOS) devices reaching their scaling limits, non-planar technologies have provided new and efficient ways to replace their planar counterparts. They offer beneficial technological solutions to scale the conventional transistors. FinFETs, Trigate, and similar non-planar devices have become popular for use in technologies for sub-14 nm gate lengths. These technologies are found to be promising for System on Chip (SoC) applications that need reduced system cost, size, and power while enjoying improved system performance.
However, this came with a price of lowered Electrostatic Discharge (ESD) robustness in these advanced technology nodes. A SoC chip in advance CMOS consists of various analog, RF and digital functional blocks, each requires dedicated ESD protection. Electrostatic Discharge is a random event, which leads to massive flow of current (in amperes) between bodies having different electrostatic potential for sub-500 ns duration. Such a high current injection can cause severe device damage by gate oxide breakdown or meltdown of device active area. Hence, it is of crucial importance to design effective ESD protection solutions in non-planar technology nodes.
There have been extensive investigations on designing several protection concepts like Diodes, Bipolar Junction Transistors (BJTs), Metal-oxide-semiconductor field effect transistors (MOSFETs) and Silicon Controlled Rectifier (SCR) in FinFET technology during the last ten years. Out of these, SCRs are suited for ESD protection in low voltage-high speed I/O as well as for ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs.
However, conventional SCRs shown in FIG. 1 suffer from very high turn-on and holding voltage, and the drawback becomes even more severe in non-planar technologies and cannot be handled by conventional approaches such as diode or transient turn-on techniques. Furthermore, conventional planar SCR design of FIG. 1 cannot be directly deployed to non-planar technologies due to technological limitations. Conventional SCRs also have poor bipolar efficiency and demonstrate weak regenerative feedback mechanism.
FIG. 2 shows (a) top view and (b) cross sectional view of a conventional SCR device (P-N-P-N) for FinFET or planar Silicon-in-Insulator (SOI) technology. Disadvantage of the SCR device of FIG. 2 is that it does not provide options for tuning its trigger or holding voltage and suffers from high on-resistance.
FIG. 3 shows a conventional gated SCR device for planar SOI technology, which can be also used for emerging technologies like FinFET. However, it suffers from disadvantage that it provides weak controllability over its turn-on voltage, and has no control over holding voltage and suffers from high on-resistance.
There are many other prior art references that provide different ways of implementing an existing SCR-like devices in planar SOI and FinFET technologies. However, such devices do not provide robust tuning capability or low trigger/holding voltage. For example, U.S. Patent application US2004/0207021A1, U.S. Pat. No. 6,909,149 B2, and U.S. patent application US2005/0212051 A1 disclose an SCR with N and P trigger taps for injecting trigger current (for tuning trigger/holding voltage) in planar SOI technology.
U.S. Pat. No. 7,943,438B2 discloses another SCR invention with N and P taps in a different scheme in order to control holding/trigger voltage in planar SOI technology.
U.S. Pat. No. 7,638,370B2 and U.S. Pat. No. 8,455,947B2 disclose techniques that may be utilized to couple a first device portion and a second device portion for use in ESD protection in FinFET technology.
U.S. Pat. No. 9,240,471B2 and U.S. Pat. No. 9,236,374B2 disclose semiconductor structures having a plurality of fins on a substrate forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins.
U.S. Pat. No. 7,135,745B1, U.S. Pat. No. 8,963,201B2, and Patent application US2014/0097465A1 disclose additional SCR inventions in bulk FinFET technology. However they all suffer from above-mentioned disadvantages.
FIG. 4 shows Fin structures based on their planar counterparts known from the prior art references. Conventional FinFET SCRs are structurally made such that anode, cathode, n-tap and p-tap are individually realized inside a well by one or more Fins (as shown FIGS. 4d & 4e) in such a way that all 4 regions are aligned along one common fin direction (FIGS. 4b & 4c).
FIG. 5 shows (a) TLP I-V characteristics and, (b) transient anode voltage vs. time characteristics of conventional bulk FinFET SCR designs as realized by simulation using 3D TCAD. The simulation results depict very high holding voltage of 6.5V. Moreover, existing SCR devices suffer from lower failure thresholds due to very high current crowding and self-heating in the Fin regions, which significantly degrades the BJT action required for SCR to trigger. FIG. 5 further shows very high turn-on voltage and absence of snapback, which depicts that conventional FinFET SCR designs have missing SCR action and, therefore, cannot be adapted for low voltage ESD protection concepts attributed to fundamental limitations of tunability within the ESD design window.
There is therefore a need in the art for a SCR design for non-planar technologies with tunable trigger and holding voltage for efficient and robust ESD protection. There is further a need for a SCR design device that has better ESD robustness per unit area.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description used in the appended claims.